1. Field of the Invention
An aspect of the present invention relates to nonvolatile memory and a manufacturing method thereof.
2. Description of the Related Art
Recently, attention has been focused on a nonvolatile memory using a ferroelectric substance, such as lead zirconate titanate (PZT: P(Zr, Ti)O3), strontium bismuth tantalite (SBT: SrBi2Ta2O9), etc, as a capacitor insulting film, because of its high speed and low power consumption characteristics.
In nonvolatile memory of the type wherein each cell transistor as a switching element is first formed and then each ferroelectric capacitor is formed thereabove through an interlayer insulating film, wiring passing through a contact hole formed in the interlayer insulating film is used as electrical connection between an upper electrode of the ferroelectric capacitor and a source/drain region of the cell transistor. (For example, refer to JP-2000-031398-A.)
The Nonvolatile memory disclosed in JP-2000-031398-A includes a transistor having a source/drain region and a gate, an insulating film formed on a semiconductor substrate so as to cover the gate and having a contact hole, a capacitor formed on the insulating film and including a lower electrode, a ferroelectric film formed on the lower electrode and an upper electrode formed on the ferroelectric film, a sidewall insulting film for covering the side faces of the lower electrode and the ferroelectric film, and wiring for electrical connection between the upper electrode and the source/drain region. The wiring is insulated from the lower electrode by the side wall insulting film and is formed to reach the source/drain region through the contact hole.
The material of the wiring is the same as that of the upper electrode at least therearound, and the upper electrode and the wiring are continuously joined.
However, for the nonvolatile memory of JP-2000-031398-A, a lithographic step to form the lower electrode and a lithographic step to form the contact hole are executed separately.
Between two steps each using masks, misalignment will occur between the first and second masks, and a margin to allow a misalignment amount is required. Consequently, integrating of nonvolatile memory is hindered.